A conventional tracking scheme in a memory, e.g., static random access memory (SRAM), has a tracking (reference) row and column placed at the bottom of a memory bit cell array. In a read tracking operation, the tracking scheme tracks the time delay along the memory array width (i.e., along a word line length), and not necessarily along the memory array height (i.e., along a bit line length).
Because of this tracking scheme, at the time when an input latch clock is reset by a tracking bit line for a new operation (i.e., to receive a new address for access in the memory), the read tracking operation may still be ongoing and not completed yet. This time delay margin issue will cause tracking function failure.
Also in the scheme known to the inventors, when a Sense Amplifier Enable (SAE) signal is triggered, it is driven from an instance center to the edge of the memory array. Thus, it takes more time for an edge sense amplifier to read data. Thus, there is extra time delay in the read tracking operation.